 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Fiber Optics Parallel Optical Link: PAROLI (R) Tx AC, 1.6 Gbit/s Parallel Optical Link: PAROLI (R) Rx AC, 1.6 Gbit/s V23814-U1306-M130 V23815-U1306-M130 Features * Power supply 3.3 V * Low voltage differential signal electrical interface (LVDS) * 12 electrical data channels * Asynchronous, AC-coupled optical link * 12 optical data channels * Transmission data rate of up to 1600 Mbit/s per channel, total link data rate up to 19 Gbit/s * 850 nm VCSEL array technology * PIN diode array technology * 62.5 m graded index multimode fiber ribbon * MT based optical port * SMD technology * Class 1 FDA and IEC Class 1 laser safety compliant Optical Port * Designed for the Simplex MT Connector (SMC) * Port outside dimensions: 15.4 mm x 6.8 mm (width x height) * MT compatible (IEC 61754-5) fiber spacing (250 m) and alignment pin spacing (4600 m) * Alignment pins fixed in module port * Integrated mechanical keying * Process plug (SMC dimensions) included with every module * Cleaning of port and connector interfaces necessary prior to mating PAROLI(R) is a registered trademark of Infineon Technologies AG Data Sheet 1 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Applications Features of the Simplex MT Connector (SMC) (as part of optional PAROLI fiber optic cables) * * * * * Uses standardized MT ferrule (IEC 61754-5) MT compatible fiber spacing (250 m) and alignment pin spacing (4600 m) Snap-in mechanism Ferrule bearing spring loaded Integrated mechanical keying Applications Telecommunication * Switching equipment * Access network Data Communication * * * * Interframe (rack-to-rack) Intraframe (board-to-board) On board (optical backplane) Interface to SCI and HIPPI 6400 standards Data Sheet 2 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Pin Configuration Pin Configuration The numbering conventions for the Tx and Rx modules are the same. Numbering Conventions Transmitter/Receiver Figure 1 Pin Description Transmitter Pin No. 1 2 3 4 5 6 Symbol Level/ Logic Description VCC t.b.l.o. t.b.l.o. t.b.l.o. t.b.l.o. LCU 7 8 9 10 11 12 13 14 15 16 VEE VEE t.b.l.o. t.b.l.o. VEE VEE DI01N DI01P VEE VEE Power supply voltage of laser driver to be left open to be left open to be left open to be left open LVCMOS Out Laser Controller Up High = normal operation Low = laser fault or -RESET low Ground Ground to be left open to be left open Ground Ground LVDS In Data Input #1, inverted LVDS In Data Input #1, non-inverted Ground Ground 3 2001-11-28 Data Sheet V23814-U1306-M130 V23815-U1306-M130 Pin Configuration Pin Description Transmitter (cont'd) Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol DI02N DI02P Level/ Logic LVDS In LVDS In Description Data Input #2, inverted Data Input #2, non-inverted Ground Ground Data Input #3, inverted Data Input #3, non-inverted Ground Ground to be left open Data Input #4, inverted Data Input #4, non-inverted Ground Data Input #5, inverted Data Input #5, non-inverted Ground Ground Data Input #6, inverted Data Input #6, non-inverted Ground Ground Data Input #7, inverted Data Input #7, non-inverted Ground Ground Data Input #8, inverted Data Input #8, non-inverted Ground Ground Ground Data Input #9, inverted Data Input #9, non-inverted to be left open VEE VEE DI03N DI03P LVDS In LVDS In VEE VEE t.b.l.o. DI04N DI04P LVDS In LVDS In LVDS In LVDS In VEE DI05N DI05P VEE VEE DI06N DI06P LVDS In LVDS In VEE VEE DI07N DI07P LVDS In LVDS In VEE VEE DI08N DI08P LVDS In LVDS In VEE VEE VEE DI09N DI09P t.b.l.o. LVDS In LVDS In Data Sheet 4 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Pin Configuration Pin Description Transmitter (cont'd) Pin No. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol Level/ Logic Description Ground Ground Data Input #10, inverted Data Input #10, non-inverted Ground Ground Data Input #11, inverted Data Input #11, non-inverted Ground Ground Data Input #12, inverted Data Input #12, non-inverted Ground Ground to be left open High = laser diode array is active Low = switches laser diode array off This input has an internal pull-down resistor to ensure laser safety switch off in case of unconnected -RESET input Ground Ground Laser ENABLE. High active. High = laser array is on if -LE is also active. Low = laser array is off. This input has an internal pull-up, therefore can be left open. Laser ENABLE. Low active. Low = laser array is on if LE is also active. This input has an internal pulldown, therefore can be left open. to be left open to be left open to be left open Power supply voltage of laser driver VEE VEE DI10N DI10P LVDS In LVDS In VEE VEE DI11N DI11P LVDS In LVDS In VEE VEE DI12N DI12P LVDS In LVDS In VEE VEE t.b.l.o. -RESET LVCMOS In 65 66 67 VEE VEE LE LVCMOS In 68 -LE 69 70 71 72 t.b.l.o. t.b.l.o. t.b.l.o. VCC Data Sheet 5 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Pin Configuration Pin Description Receiver Pin No. 1 2 3 4 5 Symbol Level/ Logic Description VEE VCC VCCO t.b.l.o. OEN 6 SD1 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 VCCO VEE t.b.l.o. VEE VEE VEE DO01P DO01N VEE VEE DO02P DO02N VEE VEE DO03P DO03N VEE VEE t.b.l.o. DO04P Ground Power supply voltage of preamplifier and analog circuitry Power supply voltage of output stages to be left open LVCMOS In Output Enable High = normal operation Low = sets all Data Outputs to low This input has an internal pull-up resistor which pulls to high level when this input is left open LVCMOS Out Signal Detect on fiber #1. High = signal of sufficient AC power is present on fiber #1 Low = signal on fiber #1 is insufficient. Power supply voltage of output stages Ground to be left open Ground Ground Ground LVDS Out Data Output #1, non-inverted LVDS Out Data Output #1, inverted Ground Ground LVDS Out Data Output #2, non-inverted LVDS Out Data Output #2, inverted Ground Ground LVDS Out Data Output #3, non-inverted LVDS Out Data Output #3, inverted Ground Ground to be left open LVDS Out Data Output #4, non-inverted 6 2001-11-28 Data Sheet V23814-U1306-M130 V23815-U1306-M130 Pin Configuration Pin Description Receiver (cont'd) Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Symbol DO04N Level/ Logic LVDS Out LVDS Out LVDS Out Description Data Output #4, inverted Ground Data Output #5, non-inverted Data Output #5, inverted Ground Ground Data Output #6, non-inverted Data Output #6, inverted Ground Ground Data Output #7, non-inverted Data Output #7, inverted Ground Ground Data Output #8, non-inverted Data Output #8, inverted Ground Ground Ground Data Output #9, non-inverted Data Output #9, inverted to be left open Ground Ground Data Output #10, non-inverted Data Output #10, inverted Ground Ground Data Output #11, non-inverted Data Output #11, inverted Ground Ground VEE DO05P DO05N VEE VEE DO06P DO06N LVDS Out LVDS Out VEE VEE DO07P DO07N LVDS Out LVDS Out VEE VEE DO08P DO08N LVDS Out LVDS Out VEE VEE VEE DO09P DO09N t.b.l.o. LVDS Out LVDS Out VEE VEE DO10P DO10N LVDS Out LVDS Out VEE VEE DO11P DO11N LVDS Out LVDS Out VEE VEE Data Sheet 7 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Pin Configuration Pin Description Receiver (cont'd) Pin No. 59 60 61 62 63 64 65 66 67 Symbol DO12P DO12N Level/ Logic LVDS Out LVDS Out Description VEE VEE VEE t.b.l.o. VEE VCCO -SD12 68 ENSD 69 70 71 72 t.b.l.o. VCC VCC VEE Data Output #12, non-inverted Data Output #12, inverted Ground Ground Ground to be left open Ground Power supply voltage of output stages LVCMOS Out Signal Detect on fiber #12 low active Low = signal of sufficient AC power is present on fiber #12 High = signal on fiber #12 is insufficient. LVCMOS In Enable Signal Detect High = SD1 and SD12 function enabled Low = SD1 and SD12 are set to permanent active. This input has an internal pull-up resistor which pulls to high level when this input is left open to be left open Power supply voltage of preamplifier and analog circuitry Power supply voltage of preamplifier and analog circuitry Ground Data Sheet 8 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Description Description PAROLI is a parallel optical link for high-speed data transmission. A complete PAROLI system consists of a transmitter module, a 12-channel fiber optic cable, and a receiver module. Transmitter V23814-U1306-M130 The transmitter module converts parallel electrical input signals via a laser driver and a Vertical Cavity Surface Emitting Laser (VCSEL) diode array into parallel optical output signals. All input data signals are Low Voltage Differential Signals (LVDS). The data rate is up to 1600 Mbit/s for each channel. The transmitter module's min. data rate DRmin depends on the disparity D and on the duty cycle of the electrical input data. If the duty cycle exceeds 57%, the channel will be shut down with a minimum response time of 1s. (See "Laser Safety Design Considerations" on Page 12). If the input duty cycle does not exceed 57%, the channel will be switched off if the input data's maximal run length of '1' bits exceeds the response time of 1 s. In the worst case the input data's maximal running length of '1' bits equals it's disparity D. From this we derive the following expression for DRmin, the minimum data rate: DRmin = D >0ELWV@ Notes: 1. The running disparity of a data stream is the difference of the number of ones and zeroes of that data stream. The disparity D is the maximum value of the running disparity for all possible starting points (with running disparity set to zero at the starting point) in the data stream. 2. The run length is the maximal number of consecutive ones or zeroes in a data stream. The run length is the disparity D. 3. Important: DRmin rate of the PAROLI link is higher than the value of DRmin of the transmitter module, as DRmin of the receiver module is higher. (See "Receiver V23815-U1306-M130" on Page 11) A logic low level at -RESET switches all laser outputs off. During power-up -RESET must be used as a power-on reset which disables the laser driver and laser control until the power supply has reached a 3 V level. The Laser Controller Up (LCU) output is low if a laser fault is detected or -RESET is forced to low. All Onondaga signals have LVCMOS levels. Transmission delay of the PAROLI system is 1 ns for the transmitter, 1 ns for the receiver and approximately 5 ns per meter for the fiber optic cable. Data Sheet 9 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Description Electrical Input 12 LVDS Input Stage 12 LE -LE laser enable Optical Output 12 Data In Laser Driver 12 Laser Diode Array Data Laser Control -RESET Laser Controller Up (LCU) Figure 2 Transmitter Block Diagram Data Sheet 10 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Description Receiver V23815-U1306-M130 The PAROLI receiver module converts parallel optical input signals into parallel electrical output signals. The optical signals received are converted into voltage signals by PIN diodes, transimpedance amplifiers, and gain amplifiers. All output data signals are Low Voltage Differential Signals (LVDS). The data rate is up to 1600 Mbit/s for each channel. The receiver module's min. data rate DRmin depends on the disparity D of the optical input data (coming fro a transmitter module). It is given by the following expression: DRmin = 81/4D >0ELWV@ Note: The running disparity of a data stream is the difference of the number of ones and zeroes of that data stream. The disparity D is the maximum value of the running disparity for all possible starting points (with running disparity set to zero at the starting point) in the data stream. Additional Signal Detect outputs (SD1 active high / SD12 active low) show whether an optical AC input signal is present at data input 1 and/or 12. The signal detect circuit can be disabled with a logic low at ENSD. The disabled signal detect circuit will permanently generate an active level at Signal Detect outputs, even if there is insufficient signal input. This could be used for test purposes. A logic low at LVDS Output Enable (OEN) sets all data outputs to logic low. SD outputs will not be effected. All non data signals have LVCMOS levels. Transmission delay of the PAROLI system is at a maximum 1 ns for the transmitter, 1 ns for the receiver and approximately 5 ns per meter for the fiber optic cable. Optical Input 12 Data Pin Diode Array 12 Amplifier 12 12 Electrical Output Gain Amplifier Signal Detect Circuit LVDS Output Stage Data out SD1 -SD12 ENSD Output Enable (OEN) Figure 3 Data Sheet Receiver Block Diagram 11 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Laser Safety Laser Safety The transmitter of the AC coupled Parallel Optical Link (PAROLI) is an FDA Class 1 laser product. It complies with FDA regulations 21 CFR 1040.10 and 1040.11. The transmitter is also an IEC Class 1 laser product as defined by IEC 60825-1 Amend. 2. To avoid possible exposure to hazardous levels of invisible laser radiation, do not exceed maximum ratings. The PAROLI module must be operated under the specified operating conditions (supply voltage between 3.0 V and 3.6 V, case temperature between 0C and 80C) under any circumstances to ensure laser safety. Attention: Class 1 Laser Product Note: Any modification of the module will be considered an act of "manufacturing," and will require, under law, recertification of the product under FDA (21 CFR 1040.10 (i)). Laser aperture and beam Figure 4 Laser Emission Laser Safety Design Considerations To ensure laser safety for all input data patterns each channel is controlled internally and will be switched off if the laser safety limits are exceeded. A channel alerter switches the respective data channel output off if the input duty cycle permanently exceeds 57%. The alerter will not disable the channel below an input duty cycle of 57% under all circumstances. The minimum alerter response time is 1 s with a constant high input, i.e. in the input pattern the time interval of excessive high input (e.g. '1's in excess of a 57% duty cycle, consecutive or non-consecutive) must not exceed 1 s, otherwise the respective channel will be switched off. The alerter switches the respective channel from off to on without the need of resetting the module if the input duty cycle is no longer violated. All of the channel alerters operate independently, i.e. an alert within a channel does not affect the other channels. To decrease the power consumption of the module unused channel inputs can be tied to high input level. In this way a portion of the supply current in this channel is triggered to shut down by the corresponding alerter. Data Sheet 12 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Technical Data Technical Data Stress beyond the values stated below may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Absolute Maximum Ratings Parameter Supply Voltage Data/Control Input Levels 1) Symbol Limit Values min. max. 4.5 -0.3 -0.5 0 -20 20 20 Unit V VCC-VEE VIN |VID| VCC+0.5 2.0 80 100 85 85 260/10 1 C/s kV % C LVDS Input Differential Voltage 2) Operating Case Temperature 3) Storage Ambient Temperature Operating Moisture Storage Moisture Soldering Conditions Temp/Time 4) ESD Resistance (all pins to VEE, human body model) 5) 1) 2) 3) 4) 5) TCASE TSTG TSOLD, tSOLD At LVDS and LVCMOS inputs. |VID| = |(input voltage of non-inverted input minus input voltage of inverted input)|. Measured at case temperature reference point (see Package Outlines Figure 15). Hot bar or hot air soldering. To avoid electrostatic damage, handling cautions similar to those used for MOS devices must be observed. Data Sheet 13 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Technical Data Recommended Operating Conditions Parameter Transmitter Power Supply Voltage Noise on Power Supply 1) Noise on Power Supply 2) LVDS Input Voltage Range 3), 4) LVDS Input Differential Voltage 5), 4) LVDS Input Skew 6) LVDS Input Rise/Fall Time 7) LVCMOS Input High Voltage LVCMOS Input Low Voltage LVCMOS Input Rise/Fall Time 8) Receiver Power Supply Voltage Noise on Power Supply Noise on Power Supply 1) 2) Symbol Limit Values min. max. 3.6 50 100 500 100 Unit VCC NPS1 NPS2 VLVDSI |VID| 3.0 V mV VCC 1000 0.5 x tR, tF ps 300 tSPN tR , tF 100 VLVCMOSIH 2.0 VLVCMOSIL VEE tR , tF VCC NPS1 NPS2 Rt 3.0 VCC 0.8 20 3.6 50 100 V ns V mV Differential LVDS Termination Impedance LVCMOS Input High Voltage LVCMOS Input Low Voltage LVCMOS Input Rise/Fall Time 8) Optical Input Rise/Fall Time 7) Input Extinction Ratio Input Center Wavelength Voltages refer to VEE = 0 V. 1) 2) 3) 4) 5) 6) 7) 8) 80 120 W V ns ps dB nm VLVCMOSIH 2.0 VLVCMOSIL VEE tR , tF tR , tF ER 5.0 820 VCC 0.8 20 400 860 lC Noise frequency is 1 kHz to 10 MHz. Voltage is peak-to-peak value. Noise frequency is > 10 MHz. Voltage is peak-to-peak value. This implies that the input stage can be AC coupled. Level diagram: see Figure 5 |VID| = |(input voltage of non-inverted input minus input voltage of inverted input)|. Skew between positive and negative inputs measured at 50% level. 20% - 80% level. Measured between 0.8 V and 2.0 V. Data Sheet 14 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Technical Data mV VCC |VID| 500 Time Figure 5 Input Level Diagram Transmitter Module VCC Data In P Rin/2 Rin/2 Data In N internal N internal P >8 K 1.95 V Figure 6 LVDS Input Stage Data Sheet 15 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Technical Data The electro-optical characteristics described in the following tables are valid only for use under the recommended operating conditions. Transmitter Electrical Characteristics Parameter Supply Current Power Consumption Data Rate per Channel LVCMOS Output Voltage Low LVCMOS Output Voltage High LVCMOS Input Current High/Low LVCMOS Output Current Low 3) LVDS Differential Input Impedance 4) LVDS Input Differential Current 1) 2) 3) 4) Symbol min. Limit Values typ. 350 1.2 1) Unit mA W Mbit/s V A mA max. 450 1.6 1600 0.4 500 0.5 4.0 120 5.0 ICC P DR VLVCMOSOL VLVCMOSOH 2.5 ILVCMOSI -500 LVCMOS Output Current High 2) ILVCMOSOH ILVCMOSOL RIN 80 |II| W mA DRmin = D [Mbit/s], with D: disparity of the input pattern. (See "Transmitter V23814-U1306-M130" on Page 9.) Source current. Sink current. LVDS input stage. Data Sheet 16 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Technical Data Transmitter Electro-Optical Characteristics Parameter Optical Rise Time Optical Fall Time 1) Symbol min. 1) Limit Values typ. max. 400 400 0.23 0.20 75 -11.0 840 -5.0 -30.0 860 2 0.85 -116 6.0 Unit ps UI ps dBm nm Random Jitter (14s) 2) Deterministic Jitter Channel-to-channel skew 3) Launched Average Power Launched Power Shutdown Center Wavelength Spectral Width (FWHM) Spectral Width (rms) Relative Intensity Noise Extinction Ratio (dynamic) Optical parameters valid for each channel. 1) 2) tR tF JR JD tCSK PAVG PSD lC Dl Dl RIN ER dB/Hz dB 3) 20% - 80% level, measured using a GBE (Gigabit Ethernet) filter. Measured with 01010... (square) optical output pattern and in module thermal steady state status. Without cooling this steady state status is reached after approximately 10 minutes. With input channel-to-channel skew 0 ps and a maximum LVDS channel-to-channel average deviation and swing deviation of 5%. VCC 3.6 V 3.135 V -RESET 2.0 V 0.8 V t3 Data data invalid t1 data valid t2 Figure 7 Timing Diagram Data Sheet 17 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Technical Data Parameter -RESET on Delay Time -RESET off Delay Time -RESET Low Duration 1) 1) Symbol Limit Values min. max. 100 50 10 Unit ms s t1 t2 t3 Only when not used as power on reset. At any failure recovery, -RESET must be brought to low level for at least t3. Receiver Electrical Characteristics Parameter Supply Current Power Consumption LVDS Output Low Voltage 1), 2) LVDS Output High Voltage 1), 2) LVDS Output Differential Voltage1), 2), 3) LVDS Rise/Fall Time 5) Symbol min. Limit Values typ. 250 0.8 925 1475 250 1125 400 1275 400 400 500 0.5 4.0 0.31 0.08 75 ps UI ps mV A mA max. 350 1.3 mA W mV Unit ICC P VLVDSOL VLVDSOH |VOD| LVDS Output Offset Voltage1), 2), 4) VOS tR , tF ILVCMOSOL LVCMOS Output Voltage Low LVCMOS Output Voltage High ILVCMOSOH 2500 LVCMOS Input Current High/Low ILVCMOSI -500 LVCMOS Output Current High 6) ILVCMOSOH LVCMOS Output Current Low 7) ILVCMOSOL JR Random Jitter (14s) 8), 9) 8) JD Deterministic Jitter 10) tCSK Channel-to-channel skew 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) Level diagram: see Figure 8 LVDS output must be terminated differentially with Rt. |VOD| = |(output voltage of non-inverted output minus output voltage of inverted output)|. VOS = 1/2 (output voltage of inverted output + output voltage of non-inverted output). Measured between 20% and 80% level with a maximum capacitive load of 5 pF. Source current Sink current With no optical input jitter. At sensitivity limit of -18.0 dBm at infinite ER. With input channel-to-channel skew 0 ps. Data Sheet 18 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Technical Data mV 1475 |VOD| 925 Time Figure 8 Output Level Diagram Receiver Electro-Optical Characteristics Parameter Data Rate Per Channel Sensitivity (Average Power) 2) Saturation (Average Power)2) Signal Detect Assert Level 3) Signal Detect Deassert Level3) Signal Detect Hysteresis 3) Return Loss of Receiver Optical parameters valid for each channel. 1) 2) 3) Symbol Limit Values min. max. 1600 -18.0 -5.0 -19.0 -28.0 1.0 12 4.0 1) Unit Mbit/s dBm DR PIN PSAT PSDA PSDD PSDA -PSDD dB ARL DRmin = 81/4D [Mbit/s], with D: disparity of the input pattern. (See "Receiver V23815-U1306-M130" on Page 11.) D 100, BER = 10-12, Extinction ratio = infinite. Extinction ratio = infinite, PSDA: Average optical power when SD switches from inactive to active. PSDD: Average optical power when SD switches from active to inactive. Data Sheet 19 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Technical Data Data Out 1, 12 t1 Signal Detect 1 t2 Signal Detect 12 Output Enable OEN 2.0 V 0.8 V Data Out data valid t3 data Low t4 data valid Figure 9 Timing Diagrams Parameter Signal Detect Deassert Time Signal Detect Assert Time LVDS Output Enable off Delay Time LVDS Output Enable on Delay Time Symbol max. 10 10 20 20 Unit s ns t1 t2 t3 t4 Data Sheet 20 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Assembly Assembly On the next pages are some figures to assist the customer in designing his printed circuit board (PCB). Figure 10 shows the mechanical dimensions of the PAROLI transmitter and receiver modules and Figure 11 to Figure 13 give the dimensions of the holes and solder pads on a customer PCB that are necessary to mount the modules on this PCB. Keeping the tolerances for the PCB given in Figure 11 to Figure 13 is required to properly attach the PAROLI transmitter and receiver module to the PCB. Attachment to the customer PCB should be done with four M2 screws torqued to 0.25 Nm +0.05 Nm (see Figure 10, cross section B-B). The screw length a should be 3 to 4 mm plus the thickness b of the customer PCB. Special care must be taken to remove residues from the soldering and washing process which can impact the mechanical function. Avoid the use of aggressive organic solvents like ketones, ethers, etc. Consult the supplier of the PAROLI modules and the supplier of the solder paste and flux for recommended cleaning solvents. The following common cleaning solvents will not affect the module: deionized water, ethanol, and isopropyl alcohol. Air-drying is recommended to a maximum temperature of 150C. Do not use ultrasonics. During soldering, heat must be applied to the leads only, to ensure that the case temperature never exceeds 150C. The module must be mounted with a hot-air or hotbar soldering process using a SnPb solder type, e.g. Sn62Pb36Ag2, in accordance with ISO 9435. Data Sheet 21 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Assembly Dimensions in [mm] inches Figure 10 Data Sheet Drawing of the PAROLI Transmitter and Receiver Module 22 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Assembly Dimensions in [mm] inches Figure 11 Recommended Circuit Board Layout: Transmitter Data Sheet 23 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Assembly Dimensions in [mm] inches Figure 12 Recommended Circuit Board Layout: Receiver No electronic components are allowed on the customer PCB within the area covered by the PAROLI module and the jumper used to attach a ribbon fiber cable. Data Sheet 24 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Assembly Dimensions in [mm] inches Figure 13 Mounting Hole, Detail Y (see Figure 11 and Figure 12) Data Sheet 25 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Assembly LVDS SMC Port PAROLI Tx module Link Controller Ribbon Cables PAROLI Rx module Board-to-Board Passive Optical Backplane PAROLI Tx Rx Optical Feed Through I/O Board Backplane PAROLI SMC Port Tx module Ribbon Cable SMC Port Rx module LVDS LVDS Point-to-Point Figure 14 Data Sheet Applications 26 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Package Outlines Package Outlines Dimensions in [mm] inches Figure 15 Data Sheet 27 2001-11-28 V23814-U1306-M130 V23815-U1306-M130 Revision History: Previous Version: Page 2001-11-28 DS0 Subjects (major changes since last revision) Document's layout has been changed: 2002-Aug. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com. Edition 2001-11-28 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 2002. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life-support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. |
Price & Availability of RXAC16GBITS
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |